Semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2 and 8F2, where F is a minimum feature size. However, DRAM is relatively slow having an access time commonly near 20 nanoseconds (“ns”). Although SRAM access time is typically an order of magnitude faster than DRAM, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, thus leading to a cell size of approximately 60F2 to 100F2.
Others have introduced memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor cell, to minimize the size of a conventional SRAM memory. A thyristor-based random access memory (“RAM”) may be effective in memory applications. Additional details regarding a thyristor-based memory cell are described in U.S. Pat. Nos. 6,767,770 B1 and 6,690,039 B1.
Charge leakage out of a thyristor-based memory cell negatively impacts the restore rate of such cell. Additional details regarding periodically pulsing a thyristor-based memory cell to restore state of such a cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504.
Content-Addressable Memory (“CAM”) is conventionally used for performing searches more rapidly than other forms of memory. CAM is used in many applications where search speed is a significant performance criterion. Some of these applications include telecommunication and computer networking switches, among other applications. A survey of CAM design is disclosed in “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey” by Kostas Pagiamtzis, et al. in the IEEE Journal of Solid-State Circuits, Vol. 41, No. 3, March 2006, pages 712-727.
A binary CAM (“BiCAM”) cell may be used to compare an incoming search word in parallel against CAM stored “match” words. Each comparison of the multiple comparisons performed in parallel gives an indication of whether or not the incoming search word matches one or more of the stored match words. In some implementations, the search word will only match one of the stored match words, known as a “one-hot” configuration. In other implementations, the search word may match more than one of the stored match words. The stored match words in the CAM are compared at the bit level with the results of such bit comparisons conventionally being either ORed (e.g., looking for any bit having a mismatch) or ANDed (e.g., looking for all bits matching).
Conventionally, a BiCAM cell includes a storage element for storing a bit of a stored match word, a circuit to compare the bit contained in the storage element against a corresponding bit of a search word, and an output driver for outputting results of the comparison onto a matchline. The circuit that compares the bit contained in the storage element, namely the bit of the match word, with a corresponding bit of a search word is an XOR circuit. Furthermore, the output driver conventionally may include either of the above-described OR or AND circuitry for comparing the individual bits outputs.
A conventional BiCAM cell may employ an SRAM storage element with NOR or NAND circuitry. A NOR-type BiCAM cell conventionally includes ten transistors, and a NAND-type BiCAM cell conventionally includes nine transistors. It should be appreciated that the XOR function in each of the NOR-type BiCAM cell and the NAND-type BiCAM cell uses differential data for both the stored match word and the search word. Furthermore, the SRAM storage element provides differential data using only one storage element in such memory cell.
A Ternary CAM (“TCAM”) cell is capable of representing any of three data states, namely a logic 1, a logic 0, and a “don't care” state. In a “don't care” state, a TCAM cell generates a “hit” regardless of the state of data on an associated searchline. A “hit” means a match between a search bit and a stored match bit (“match bit”). A TCAM cell allows a bit in a match word to be ignored as part of a search operation. Thus, a TCAM cell allows bit masking as part of the function of such cell, which is useful in some CAM applications.
For a NOR-type TCAM cell, the storage capability of the cell is bifurcated by using two storage elements in a TCAM cell. However, a conventional TCAM cell suffers from a substantial area penalty compared to a conventional BiCAM cell because two storage elements are used for each cell. A conventional NOR-type TCAM cell may include 14 transistors. A DRAM-based TCAM cell using 6 transistors and 2 capacitors is described in additional detail in “eDRAM-Based TCAM Cell” by Noda et al. in the IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, January 2005, paged 245-253.
Others have suggested using static thyristor-based cells for CAM, as disclosed in U.S. Pat. No. 6,845,026. However, static thyristor-based cell arrays, while smaller than SRAM-based CAM arrays of equivalent capacity, are still relatively large.
As is known, conventional CAM may have significantly large power consumption. Others have considered using precomputation to reduce CAM power consumption, as disclosed in “A Low-Power Precomputation-Based Fully Parallel Content-Addressable Memory” by Chi-Sheng Lin, et al. in the IEEE Journal of Solid-State Circuits, Vol. 38, No. 4, April 2003, pages 654-662.